1. Field of the Invention
The invention relates to integrated circuit devices and more particularly to enhancing dielectric material in those device.
2. Description of Related Art
One way to improve integrated circuit performance is through scaling the individual devices that comprise the integrated circuit. Thus, each subsequent generation of integrated circuit generally involves reducing the size of the individual devices on, for example, a semiconductor chip. The Morse rule is a common benchmark in the integrated circuit technology and provides that devices will be scaled down or reduced in size by one-third for each new generation.
The scale of a transistor device requires consideration of the desired performance of the device. For example, one goal may be to increase the current flow in the semiconductor material of the transistor. The current flow is proportional to the voltage applied to the gate electrode and the capacitance seen at the gate:Q∝C(V−Vth)where Q is one measure of the current flow, C is capacitance, V is the voltage applied to the gate electrode, and Vth is the threshold voltage of the device.
To increase the voltage applied to a device requires an increase in power, P (P∝V2). However, at the same time as increasing the charge in the transistor, subsequent generations also seek to reduce the power required to run the device, since, importantly, a reduction of power reduces the heat generated by the device. Thus, to increase the current flow through the device without increasing the power requires an increase in the capacitance in the gate.
One way to increase the capacitance is by adjusting the thickness of the gate dielectric. In general, the capacitance is related to the gate dielectric by the following formula:C=kox/telectrical where kox is the dielectric constant of silicon dioxide (SiO2) and telectrical is the electrical thickness of the gate dielectric. The electrical thickness of the gate dielectric is greater than the actual thickness of the dielectric in most semiconductor devices. In general, as carriers flow through the channel of a semiconductor-based transistor device there is a quantum effect experienced in the channel which causes an area directly below the gate to become insulative. The insulative region acts like an extension of the gate dielectric by essentially extending the dielectric into a portion of the channel. The second cause of increase gate dielectric thickness attributable to telectrical is experienced by a similar phenomenon happening in the gate electrode itself. At inversion, a gate electrode of polysilicon, for example, will generally experience a depletion of carriers in the area of the polysilicon near the gate dielectric. Accordingly, the gate dielectric appears to extend into the polysilicon gate electrode.
The result of the quantum effect in the channel and a depletion in the polysilicon gate electrode is an electrical thickness (telectrical) of the gate dielectric greater than the actual thickness of the gate dielectric. The magnitude of the channel quantum effect and polysilicon depletion may be estimated or determined for a given technology. Accordingly, the electrical thickness (telectrical) for a SiO2 may be calculated and scaled for a given technology.
In considering the capacitance effects of the gate dielectric, a consideration of the thickness of gate dielectric is important for other reasons. First, the gate dielectric cannot be too thin as a thin gate dielectric will allow a leakage current from the channel through the gate electrode. At the same time, the gate dielectric cannot be too thick because such a gate structure may produce an undesirable fringe electric field. The desired electric field at the gate is typically perpendicular to the surface of the semiconductor substrate. Beyond a certain gate dielectric thickness, generally thought to be beyond one-third the lateral width of the gate electrode for a SiO2 gate dielectric, the electrical field deviates from a perpendicular course and sprays about the gate electrode leading to an undesirable fringe electric field.
What is needed is a way to increase the capacitance of a gate dielectric without decreasing the performance of the device. It is preferable if the increased capacitance is consistent with scaling techniques and may be used in multiple generation technologies.